Motorola MVME172 - Manual (Page 211)

Programming Model
http://www.mcg.mot.com/literature 3-23
3
SCC Interrupt Control Register
IL2-IL0 These three bits select the interrupt level for the SCC
controller. Level 0 does not generate an interrupt.
IEN When this bit is set high, the interrupt is enabled. The
interrupt is disabled when this bit is low.
INT This bit reflects the state of the INT pin from either
Z85230 controller (qualified by the IEN bit). When this
bit is high, an SCC controller interrupt is being generated
at the level programmed in IL2-IL0. When the interrupt is
cleared in the Z85230, INT returns to zero. During the
interrupt acknowledge cycle, interrupts from the first
Z85230 have priority over those from the second Z85230.
ADR/SIZ $FFF4201C (8 bits)
BIT 23 22 21 20 19 18 17 16
NAME INT IEN IL2 IL1 IL0
OPER R R R R/W R R/W R/W R/W
RESET 0 0 0 PL 0 PL 0 0 PL 0 PL 0 PL