Artesyn ATCA-7350 Installation and Use (September 2014) - Manual (Page 93)

Functional Description
ATCA-7350 Installation and Use (6806800G59G) 93
Figure 4-4 shows the relationship between the two WDTs.
4.10.1 WDT#1
System software and host BIOS communicate with the IPMC through the keyboard controller
style (KCS) interface. The host processor sends a "Reset WDT message" to the IPMC through the
KCS interface. The timeout threshold of WDT#1 varies with system running status. Here, in the
below figure SMS means System Management Software.
The WDT#1 takes different actions in different phases, see as follows:
1. Before BIOS POST: Before moment  as shown in Figure 4-5 , the host processor does not
run. The IPMC software records the time period from system reset completion to the
arrival time of the first "Reset WDT message". If the "Reset WDT message" does not arrive
within 40 s, the WDT times out. In this case, the IPMC sends a system reset message.
2. BIOS POST phase: the time period from

to

as shown in Figure 4-5 . In the BIOS POST
phase, the "Reset WDT message" is sent by the BIOS software of the host processor.
Figure 4-4 Relationship between the two WDTs
Figure 4-5 WDT operating status