Artesyn ATCA-7350 Installation and Use (September 2014) - Manual (Page 170)

Addressing
ATCA-7350 Installation and Use (6806800G59G) 170
9.2.2 Configuration Data Register MCH CONFIG_ADDRESS
I/O Address: 0x0CFC
Default Value: 0x0000000
Access: Read/Write
Size: 32 bits
CONFIG_DATA is a 32-bit read/write window into the PCI configuration space. The portion of
configuration space that is referenced by CONFIG_DATA is determined by the contents of
CONFIG_ADDRESS.
9.3 I/O Address Assignments
I/O port addresses are divided among the on-board devices. Please refer to the respective
device specifications for specific I/O address usage. These devices include the ESB2, MCH,
82571 Ethernet controller, XGI Z9 VGA controller, Broadcom 5715 Ethernet controller, LSI
1064 SAS controller.
The MCH uses only I/O ports 0xCF8 and 0xCFC for PCI configuration cycle generation. These
registers are shown in "Configuration Address Register MCH CONFIG_ADDRESS" on section
3.2.1 and "Configuration Data Register MCH CONFIG_ADDRESS" on section 3.2.2. The ESB2
forwards applicable I/O transactions to its attached PCI buses. The "I/O Address Cross-
references" table lists document references to I/O descriptions.
Table 9-4 Configuration data register bit assignments
Bit Description
31:0 Configuration Data Window (CDW): If bit 31 of CONFIG_ADDRESS is set to 1, any I/O access
to the CONFIG_DATA register is mapped to configuration space pointed to by the contents of
CONFIG_ADDRESS.
Table 9-5 I/O address cross-references
Device Document Title/Number Section/Page/Table
ESB2 ESB2 EDS Section 11.4, Table 11-4
MCH Intel® 5000 Chipset MCH EDS Section 3.5 Table 3-5, 3-6 and Section 3.6 Table 3-7