Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual
Stratix v avalon-mm interface for pcie solutions, User guide
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Table of contents
Document Outline
- Stratix V Avalon-MM Interface for PCIe Solutions User Guide
- 1. Datasheet
- 2. Getting Started with the Avalon‑MM Stratix V Hard IP for PCI Express
- 3. Parameter Settings
- 4. 64- or 128-Bit Avalon-MM Interface to the Application Layer
- 5. Registers
- Correspondence between Configuration Space Registers and the PCIe Specification
- Type 0 Configuration Space Registers
- Type 1 Configuration Space Registers
- PCI Express Capability Structures
- Altera-Defined VSEC Registers
- CvP Registers
- 64- or 128-Bit Avalon-MM Bridge Register Descriptions
- Avalon-MM to PCI Express Interrupt Registers
- Avalon-MM to PCI Express Interrupt Status Registers
- Avalon-MM to PCI Express Interrupt Enable Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Control Register Access (CRA) Avalon-MM Slave Port
- Avalon-MM to PCI Express Interrupt Registers
- Programming Model for Avalon‑MM Root Port
- Uncorrectable Internal Error Mask Register
- Uncorrectable Internal Error Status Register
- Correctable Internal Error Mask Register
- Correctable Internal Error Status Register
- 6. Reset and Clocks
- 7. Interrupts for Endpoints
- 8. Error Handling
- 9. IP Core Architecture
- Top-Level Interfaces
- Avalon-MM Interface
- Clocks and Reset
- Transceiver Reconfiguration
- Interrupts
- PIPE
- Data Link Layer
- Physical Layer
- 32-Bit PCI Express Avalon-MM Bridge
- Avalon‑MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
- Completer Only Single Dword Endpoint
- 10. Transceiver PHY IP Reconfiguration
- 11. Throughput Optimization
- 12. Design Implementation
- 13. Optional Features
- 14. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- B. Lane Initialization and Reversal
- C. Additional Information