Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual
Page 37
Table 4-2: Avalon-MM RX Master Interface Signals
Signals that include Bar number 0 also exist for BAR1–BAR5 when additional BARs are enabled.
Signal Name
Direction
Description
RxmWrite
Output
Asserted by the core to request a write to an Avalon-
MM slave.
RxmAddress_
Output
The address of the Avalon-MM slave being accessed.
RxmWriteData_
Output
RX data being written to slave.
full-featured IP core.
IP core.
RxmByteEnable_
Output
Byte enable for write data.
RXMBurstCount_
5:0]
Output
The burst count, measured in qwords, of the RX write or
read request. The width indicates the maximum data
that can be requested. The maximum data in a burst is
512 bytes.
RXMWaitRequest_
Input
Asserted by the external Avalon-MM slave to hold data
transfer.
RXMRead_
Output
Asserted by the core to request a read.
RXMReadData_
Input
Read data returned from Avalon-MM slave in response
to a read request. This data is sent to the IP core through
the TX interface.
IP core.
RXMReadDataValid_
Input
Asserted by the system interconnect fabric to indicate
that the read data on is valid.
RxmIrq_
,
Input
Indicates an interrupt request asserted from the system
interconnect fabric. This signal is only available when
the CRA port is enabled. Qsys-generated variations have
as many as 16 individual interrupt signals (
rxm_irq_
is asserted on consecutive cycles
without the deassertion of all interrupt inputs, no MSI
message is sent for subsequent interrupts. To avoid
losing interrupts, software must ensure that all interrupt
sources are cleared for each MSI message received.
The following figure illustrates the RX master port propagating requests to the Application Layer and also
shows simultaneous, DMA read and write activity
4-4
RX Avalon-MM Master Signals
UG-01097_avmm
2014.12.15
Altera Corporation
64- or 128-Bit Avalon-MM Interface to the Application Layer