Altera Stratix V Avalon-MM Interface for PCIe Solutions - Manual (Page 20)

a. In the
/ep_g2x4_avmm128/synth/
, open ep_g2x4_avmm128.v.
b. Comment out the declaration for
pcie_a10_hip_0_hip_ctrl_test_in
.
c. Add a wire
[31:0] pcie_a10_hip_0_hip_ctrl_test_in
declaration to the same the same file.
d. Assign
pcie_a10_hip_0_hip_ctrl_test_in
= 0x000000A8.
e. Connect
pcie_a10_hip_0_hip_ctrl_test_in
to the
test_in
port on the Stratix V Hard IP for
PCI Express instance.
2. On the Quartus II Processing menu, click Start Compilation.
3. After compilation, expand the TimeQuest Timing Analyzer folder in the Compilation Report. Note
whether the timing constraints are achieved in the Compilation Report.
If your design does not initially meet the timing constraints, you can find the optimal Fitter settings for
your design by using the Design Space Explorer. To use the Design Space Explorer, click Launch Design
Space Explorer on the Tools menu.
Programming a Device
After you compile your design, you can program your targeted Altera device and verify your design in
hardware.
For more information about programming Altera FPGAs, refer to Quartus II Programmer.
Related Information
Quartus II Programmer
Understanding Channel Placement Guidelines
Stratix V transceivers are organized in banks of six channels. The transceiver bank boundaries are
important for clocking resources, bonding channels, and fitting. Refer to the channel placement figures
following Serial Interface Signals for illustrations of channel placement for x1, x2, x4, and x8 variants.
Related Information
Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices on page 4-29
2-8 Programming a Device
UG-01097_avmm
2014.12.15
Altera Corporation Getting Started with the Avalon‑MM Stratix V Hard IP for PCI Express
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