Base address register (bar) settings – Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual
Page 23
Parameter
Value
Description
Use 62.5 MHz
application clock
On/Off
This mode is only available only for Gen1 ×1.
Enable configu‐
ration via PCI
Express (CvP)
On/Off
When On, the Quartus II software places the Endpoint in the
location required for configuration via protocol (CvP). For
more information about CvP, click the Configuration via
Protocol (CvP) link below.
Use ATX PLL
On/Off
When enabled, the Hard IP for PCI Express uses the ATX PLL
instead of the CMU PLL. For other configurations, using the
ATX PLL instead of the CMU PLL reduces the number of
transceiver channels that are necessary. This option requires
the use of the soft reset controller and does not support the
CvP flow.
Enable Hard IP
reset pulse at
power-up when
using the soft
reset controller
On/Off
When On, the soft reset controller generates a pulse at power
up to reset the Hard IP. This pulse ensures that the Hard IP is
reset after programming the device, regardless of the behavior
of the dedicated PCI Express reset pin,
perstn
. This option is
available for Gen2 and Gen3 designs that use a soft reset
controller.
Related Information
Base Address Register (BAR) Settings
You can configure up to six 32-bit BARs or three 64-bit BARs.
Table 3-2: BAR Registers
Parameter
Value
Description
Type
Disabled
64-bit prefetchable memory
32-bit non-prefetchable memory
32-bit prefetchable memory
I/O address space
Defining memory as prefetchable allows data in the
region to be fetched ahead anticipating that the
requestor may require more data from the same
region than was originally requested. If you specify
that a memory is prefetchable, it must have the
following 2 attributes:
• Reads do not have side effects
• Write merging is allowed
The 32-bit prefetchable memory and I/O address
space BARs are only available for the Legacy
Endpoint.
UG-01097_avmm
2014.12.15
Base Address Register (BAR) Settings
3-3
Parameter Settings
Altera Corporation