Altera Stratix V Avalon-MM Interface for PCIe Solutions - Manual (Page 19)

Generating Quartus II Synthesis Files
1. On the Generate menu, select Generate HDL.
2. For Create HDL design files for synthesis, select Verilog.
You can leave the default settings for all other items.
3. Click Generate to generate files for Quartus II synthesis.
4. Click Finish when the generation completes.
Creating a Quartus II Project
You can create a new Quartus II project with the New Project Wizard, which helps you specify the
working directory for the project, assign the project name, and designate the name of the top-level design
entity.
1. On the Quartus II File menu, click then New Project Wizard, then Next.
2. Click Next in the New Project Wizard: Introduction (The introduction does not appear if you
previously turned it off.)
3. On the Directory, Name, Top-Level Entity page, enter the following information:
a. For What is the working directory for this project, browse to
/ep_g2x4/synthesis/ .
b. For What is the name of this project, select ep_g2x4.v from the synthesis directory.
4. Click Next.
5. On the Add Files page, add
/ep_g2x4/synthesis/ep_g2_x4.qip to your Quartus II project. This
file lists all necessary files for Quartus II compilation.
6. Click Next to display the Family & Device Settings page.
7. On the Device page, choose the following target device family and options:
a. In the Family list, select Stratix V (GS/GT/GX/E).
b. In the Devices list, select Stratix V GX PCIe.
c. In the Available devices list, select 5SGXEA7K2F40C2.
8. Click Next to close this page and display the EDA Tool Settings page.
9. From the Simulation list, select ModelSim. From the Format list, select the HDL language you intend
to use for simulation.
10.Click Next to display the Summary page.
11.Check the Summary page to ensure that you have entered all the information correctly.
Compiling the Design
1. Before compiling, you need to make a few changes to your top-level Verilog HDL file to create a design
that you can successfully download to a PCB.
UG-01097_avmm
2014.12.15
Generating Quartus II Synthesis Files 2-7
Getting Started with the Avalon‑MM Stratix V Hard IP for PCI Express Altera Corporation
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