Minimizing bar sizes and the pcie address space – Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual
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Minimizing BAR Sizes and the PCIe Address Space
For designs that include multiple BARs, you may need to modify the base address assignments
auto-assigned by Qsys in order to minimize the address space that the BARs consume. For example,
consider a Qsys system with the following components:
• Offchip_Data_Mem DDR3 (SDRAM Controller with UniPHY) controlling 256 MBytes of memory—
Qsys auto-assigned a base address of 0x00000000
• Quick_Data_Mem (On-Chip Memory (RAM or ROM)) of 4 KBytes—Qsys auto-assigned a base
address of 0x10000000
• Instruction_Mem (On-Chip Memory (RAM or ROM)) of 64 KBytes—Qsys auto-assigned a base
address of 0x10020000
• PCIe (Avalon-MM Stratix V Hard IP for PCI Express)
• Cra (Avalon-MM Slave)—auto assigned base address of 0x10004000
• Rxm_BAR0 connects to Offchip_Data_Mem DD R3 avl
• Rxm_BAR2 connects to Quick_Data_Mem s1
• Rxm_BAR4 connects to PCIe. Cra Avalon MM Slave
• Nios2 (Nios
®
II Processor)
• data_master connects to PCIe Cra, Offchip_Data_Mem DDR3 avl, Quick_Data_Mem s1,
Instruction_Mem s1, Nios2 jtag_debug_module
• instruction_master connects to Instruction_Mem s1
UG-01097_avmm
2014.12.15
Minimizing BAR Sizes and the PCIe Address Space
9-15
IP Core Architecture
Altera Corporation