Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual
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Parameter
Value
Description
of flow control credits. You can set the Maximum payload
size parameter on the Device tab.
The Message window dynamically updates the number of
credits for Posted, Non-Posted Headers and Data, and
Completion Headers and Data as you change this selection.
• Minimum—configures the minimum PCIe specification
allowed for non-posted and posted request credits, leaving
most of the RX Buffer space for received completion
header and data. Select this option for variations where
application logic generates many read requests and only
infrequently receives single requests from the PCIe link.
• Low—configures a slightly larger amount of RX Buffer
space for non-posted and posted request credits, but still
dedicates most of the space for received completion header
and data. Select this option for variations where application
logic generates many read requests and infrequently
receives small bursts of requests from the PCIe link. This
option is recommended for typical endpoint applications
where most of the PCIe traffic is generated by a DMA
engine that is located in the endpoint application layer
logic.
• Balanced—configures approximately half the RX Buffer
space to received requests and the other half of the RX
Buffer space to received completions. Select this option for
variations where the received requests and received
completions are roughly equal.
Reference clock
frequency
100 MHz
125 MHz
The PCI Express Base Specification 3.0 requires a
100 MHz ±300 ppm reference clock. The 125 MHz reference
clock is provided as a convenience for systems that include a
125 MHz clock source. For more information about Gen3
operation, refer to 4.3.8 Refclk Specifications for 8.0 GT/sin the
specification.
For Gen3, Altera recommends using a common reference
clock (0 ppm) because when using separate reference clocks
(non 0 ppm), the PCS occasionally must insert SKP symbols,
potentially causes the PCIe link to go to recovery. Stratix V
PCIe Hard IP in Gen1 or Gen2 modes are not affected by this
issue. Systems using the common reference clock (0 ppm) are
not affected by this issue. The primary repercussion of this is a
slight decrease in bandwidth. On Gen3 x8 systems, this
bandwidth impact is negligible. If non 0 ppm mode is
required, so that separate reference clocks are being used,
please contact Altera for further information and guidance.
3-2
Stratix V and Arria V GZ Avalon-MM System Settings
UG-01097_avmm
2014.12.15
Altera Corporation
Parameter Settings