Altera Stratix V Avalon-MM Interface for PCIe Solutions - Manual (Page 35)

Figure 4-1: 64- or 128-Bit Avalon-MM Interface to the Application Layer
tx_out0[:0]
rx_in0[:0]
1-Bit Serial
cra_readdata[31:0]
cra_waitrequest
cra_byteenable[3:0]
cra_chipselect
cra_address[11:0]
cra_read
cra_write
cra_writedata[31:0]
txs_writedata[-1:0]
txs_busrtcount[6:0]
txs_chipselect
txs_read
txs_write
txs_address[-1:0]
txs_byteenable[7:0]
txs_readdatavalid
txs_readdata[-1:0]
txs_waitrequest
32-Bit
Avalon-MM
CRA
Slave Port
(Optional,
Not available for
Completer-Only
Single Dword)
64- or 128-Bit
Avalon-MM TX
Slave Port
(Not used for
Completer-Only)
Test
Interface
test_in[31:0]
simu_mode_pipe
rxm_bar0_write_
rxm_bar0_address_[31:0]
rxm_bar0_writedata_[63:0] or [31:0]
rxm_bar0_byteenable_[7:0]
rxm_bar0_burstcount_[6:0]
rxm_bar0_waitrequest_
rxm_bar0_read_
rxm_bar0_readdata_[63:0]
rxm_bar0_readdatavalid
rxm_irq[:0], < 16
reconfig_from_xcvr[46-1:0]
MsiIntfc_o[81:0]
MsiControl_o[15:0]
MsixIntfc_o[15:0]
IntxReq_i
IntxAck_o
reconfig_to_xcvr[70-1:0]
Transceiver
Multiple
MSI/MSI-X
Hard IP
Status
Extension
Reconfiguration
Clocks
npor
nreset_status
pin_perst
cfg_par_err
derr_cor_ext_rcv
derr_ext_rpl
derr_rpl
dlup
dlup_exit
ev128ns
ev1us
hotrst_exit
int_status[3:0]
ko_cpl_spc_data[11:0]
ko_cpl_spc_header[7:0]
l2_ext
lane_act[3:0]
ltssmstate[4:0]
rx_par_err
tx_par_err
Reset &
Lock Status
refclk
coreclkout
cra_irq_irq
txdata0[7:0]
txdatak0
txblkst0
rxdata0[7:0]
rxdatak0
rxblkst0
txdetectrx0
txelecidle0
txcompl0
rxpolarity0
powerdown0[1:0]
currentcoeff0[17:0]
currentrxpreset0[2:0]
txmargin[2:0]
txswing
txsynchd0[1:0]
rxsyncd[1:0]
rxvalid0
phystatus0
rxelecidle0
rxstatus0[2:0]
simu_mode_pipe
sim_pipe_rate[1:0]
sim_pipe_pclk_in
sim_pipe_pclk_out
sim_pipe_clk250_out
sim_pipe_clk500_out
sim_ltssmstate[4:0]
rxfreqlocked0
rxdataskip0
eidleinfersel0[2:0]
txdeemph0
Transmit Data
Interface Signals
Receive Data
Interface Signals
Command
Interface Signals
Status
Interface Signals
64- or 128-Bit Avalon-MM Intearface to
Application Layer
PIPE
Interface
for Simulation
and Hardware
Debug Using
dl_ltssm[4:0]
SignalTap,
Gen3 version
pld_clk_inuse
pme_to_sr
rx_st_bar[7:0]
rx_st_data[127:0]
rx_st_eop
rx_st_err
rx_st_sop
rx_st_valid
serr_out
tl_cfg_add[3:0]
tx_cfg_sts[52:0]
tx_st_ready
Hard IP Reset,
Status and
Link Training
64-Bit
Avalon-MM RX
BAR Master Port
Note: Signals listed for BAR0 are the same as those for BAR1–BAR5 when those BARs are enabled in the
parameter editor.
Variations using the Avalon-MM interface implement the Avalon-MM protocol described in the Avalon
Interface Specifications. Refer to this specification for information about the Avalon-MM protocol,
including timing diagrams.
Related Information
Avalon Interface Specifications
4-2 64- or 128-Bit Avalon-MM Interface to the Application Layer
UG-01097_avmm
2014.12.15
Altera Corporation 64- or 128-Bit Avalon-MM Interface to the Application Layer
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