Altera Stratix V Avalon-MM Interface for PCIe Solutions - Manual (Page 177)

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2014.12.15
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Revision History for the Avalon-MM Interface
Date Version Changes Made
2014.12.15 14.1 Made the following changes to the user guide:
• Added statement that the bottom left hard IP block includes the
CvP functionality for flip chip packages. For other package types,
the CvP functionality is in the bottom right block.
• Corrected bit definitions for
CvP Status
register.
• Updated definition of
CVP_NUMCLKS
in the
CvP Mode Control
register.
• Added definitions for
test_in[2]
,
test_in[6]
and
test_in[7]
.
• Added note that for Root Ports, when the Slot Power register is
enabled, the Command Completed Interrupt Enable bit of the Slot
Control register remains Read/Write. It should be hardwired to
1'b0.
• Removed requirement that
TxsWrite_i
be asserted continuously
throughout a write burst.
TxsWrite_i
may be deasserted and
reasserted during a burst.
• Added figure showing connectivity for the Transceiver Reconfigu‐
ration Controller and Altera PCIe Reconfig Driver IP Cores to the
Gettting Started chapter.
• Removed Maximum and High settings from the RX Buffer credit
allocation -performance for received requests setting. These
settings are not available for the Avalon-MM interface and could
lead to data corruption.
• Revised Receiving a Completion TLP under Programming Model
for Avalon-MM Root Port to cover read and non-posted
completions.
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