Altera Stratix V Avalon-MM Interface for PCIe Solutions - Manual (Page 69)

Test Signals
Table 4-16: Test Interface Signals
The
test_in
bus provides run-time control and monitoring of the internal state of the IP core.
Signal Direction Description
test_in[31:0] Input The bits of the
test_in
bus have the following definitions:
• [0]: Simulation mode. This signal can be set to 1 to accelerate
initialization by reducing the value of many initialization
counters.
• [1]: Reserved. Must be set to 1’b0
• [2]: Descramble mode disable. This signal must be set to 1
during initialization in order to disable data scrambling. You
can use this bit in simulation for both Endpoints and Root
Ports to observe descrambled data on the link. Descrambled
data cannot be used in open systems because the link partner
typically scrambles the data.
• [4:3]: Reserved. Must be set to 4’b01.
• [5]: Compliance test mode. Disable/force compliance mode.
When set, prevents the LTSSM from entering compliance
mode. Toggling this bit controls the entry and exit from the
compliance state, enabling the transmission of Gen1, Gen2
and Gen3 compliance patterns.
• [6]: Forces entry to compliance mode when a timeout is
reached in the polling.active state and not all lanes have
detected their exit condition.
• [7]: Disable low power state negotiation. Altera recommends
setting thist bit.
• [31:8]: Reserved. Set to all 0s.
For more information about using the
test_in
to debug, refer to
the Knowledge Base Solution How can I observe the Hard IP for
PCI Express PIPE interface signals for Arria V GZ and Stratix V
devices? in the Related Links below.
Related Information
How can I observe the Hard IP for PCI Express PIPE interface signals for Arria V GZ and Stratix V
devices?
4-36 Test Signals
UG-01097_avmm
2014.12.15
Altera Corporation 64- or 128-Bit Avalon-MM Interface to the Application Layer
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