Altera Stratix V Avalon-MM Interface for PCIe Solutions - Manual (Page 128)

PIPE
The PIPE interface implements the Intel-designed PIPE interface specification. You can use this parallel
interface to speed simulation; however, you cannot use the PIPE interface in actual hardware.
• The Gen1, Gen2, and Gen3 simulation models support PIPE and serial simulation.
• For Gen3, the Altera BFM bypasses Gen3 Phase 2 and Phase 3 Equalization. However, Gen3 variants
can perform Phase 2 and Phase 3 equalization if instructed by a third-party BFM.
Related Information
PIPE Interface Signals on page 4-31
Data Link Layer
The Data Link Layer is located between the Transaction Layer and the Physical Layer. It maintains packet
integrity and communicates (by DLL packet transmission) at the PCI Express link level (as opposed to
component communication by TLP transmission in the interconnect fabric).
The DLL implements the following functions:
• Link management through the reception and transmission of DLL packets (DLLP), which are used for
the following functions:
• Power management of DLLP reception and transmission
• To transmit and receive
ACK
/
NACK
packets
• Data integrity through generation and checking of CRCs for TLPs and DLLPs
• TLP retransmission in case of
NAK
DLLP reception using the retry buffer
• Management of the retry buffer
• Link retraining requests in case of error through the Link Training and Status State Machine
(LTSSM) of the Physical Layer
9-4 PIPE
UG-01097_avmm
2014.12.15
Altera Corporation IP Core Architecture
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