Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual
Page 17
# INFO: 36168 ns EP PCI Express Link Control Register (0040):
# INFO: 36168 ns Common Clock Config: System Reference Clock Used
# INFO: 37960 ns EP PCI Express Capabilities Register (0002):
# INFO: 37960 ns Capability Version: 2
# INFO: 37960 ns Port Type: Native Endpoint
# INFO: 37960 ns EP PCI Express Device Capabilities Register(00008020):
# INFO: 37960 ns Max Payload Supported: 128 Bytes
# INFO: 37960 ns Extended Tag: Supported
# INFO: 37960 ns Acceptable L0s Latency: Less Than 64 ns
# INFO: 37960 ns Acceptable L1 Latency: Less Than 1 us
# INFO: 37960 ns Attention Button: Not Present
# INFO: 37960 ns Attention Indicator: Not Present
# INFO: 37960 ns Power Indicator: Not Present
# INFO: 37960 ns EP PCI Express Link Capabilities Register (01406041):
# INFO: 37960 ns Maximum Link Width: x4
# INFO: 37960 ns Supported Link Speed: 2.5GT/s
# INFO: 37960 ns L0s Entry: Not Supported
# INFO: 37960 ns L1 Entry: Not Supported
# INFO: 37960 ns L0s Exit Latency: 2 us to 4 us
# INFO: 37960 ns L1 Exit Latency: Less Than 1 us
# INFO: 37960 ns Port Number: 01
# INFO: 37960 ns Surprise Dwn Err Report: Not Supported
# INFO: 37960 ns DLL Link Active Report: Not Supported
# INFO: 37960 ns EP PCI Express Device Capabilities 2 Register (0000001F):
# INFO: 37960 ns Completion Timeout Rnge: ABCD (50us to 64s)
# INFO: 39512 ns EP PCI Express Device Control Register (0110):
# INFO: 39512 ns Error Reporting Enables: 0
# INFO: 39512 ns Relaxed Ordering: Enabled
# INFO: 39512 ns Error Reporting Enables: 0
# INFO: 39512 ns Relaxed Ordering: Enabled
# INFO: 39512 ns Max Payload: 128 Bytes
# INFO: 39512 ns Extended Tag: Enabled
# INFO: 39512 ns Max Read Request: 128 Bytes
# INFO: 39512 ns EP PCI Express Device Status Register (0000):
# INFO: 41016 ns EP PCI Express Virtual Channel Capability:
# INFO: 41016 ns Virtual Channel: 1
# INFO: 41016 ns Low Priority VC: 0
# INFO: 46456 ns BAR Address Assignments:
# INFO: 46456 ns BAR Size Assigned Address Type
# INFO: 46456 ns BAR1:0 4 MBytes 00000001 00000000 Prefetchable
# INFO: 46456 ns BAR2 32 KBytes 00200000 Non-Prefetchable
# INFO: 46456 ns BAR3 Disabled
# INFO: 46456 ns BAR4 Disabled
# INFO: 46456 ns BAR5 Disabled
# INFO: 46456 ns ExpROM Disabled
# INFO: 48408 ns Completed configuration of Endpoint BAR
# INFO: 50008 ns Starting Target Write/Read Test.
# INFO: 50008 ns Target BAR = 0
# INFO: 50008 ns Length = 000512, Start Offset = 000000
# INFO: 54368 ns Target Write and Read compared okay!
# INFO: 54368 ns Starting DMA Read/Write Test.
# INFO: 54368 ns Setup BAR = 2
# INFO: 54368 ns Length = 000512, Start Offset = 000000
# INFO: 60609 ns Interrupt Monitor: Interrupt INTA Asserted
# INFO: 60609 ns Clear Interrupt INTA
# INFO: 62225 ns Interrupt Monitor: Interrupt INTA Deasserted
# INFO: 69361 ns MSI recieved!
# INFO: 69361ns DMA Read and Write compared okay!
# SUCCESS: Simulation stopped due to successful completion! # Break
at .ep_g1x4_tb/simulation/submodules//altpcietb_bfm_log.v line 78
Related Information
UG-01097_avmm
2014.12.15
Generating the Example Design
2-5
Getting Started with the Avalon‑MM Stratix V Hard IP for PCI Express
Altera Corporation