Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual
Page 44
Signal
Direction
Description
derr_cor_ext_rpl
Output
Indicates a corrected ECC error in the retry buffer. This signal is
for debug only. Because the error was corrected by the IP core,
no Application Layer intervention is required.
(3)
derr_rpl
Output
Indicates an uncorrectable error in the retry buffer. This signal is
for debug only.
(3)
dlup
Output
When asserted, indicates that the Hard IP block is in the Data
Link Control and Management State Machine (DLCMSM) DL_
Up state.
dlup_exit
Output
This signal is asserted low for one
pld_clk
cycle when the IP
core exits the DLCMSM DL_Up state, indicating that the Data
Link Layer has lost communication with the other end of the
PCIe link and left the Up state. When this pulse is asserted, the
Application Layer should generate an internal reset signal that is
asserted for at least 32 cycles.
ev128ns
Output
Asserted every 128 ns to create a time base aligned activity.
ev1us
Output
Asserted every 1µs to create a time base aligned activity.
hotrst_exit
Output
Hot reset exit. This signal is asserted for 1 clock cycle when the
LTSSM exits the hot reset state. This signal should cause the
Application Layer to be reset. This signal is active low. When this
pulse is asserted, the Application Layer should generate an
internal reset signal that is asserted for at least 32 cycles.
int_status[3:0]
Output
These signals drive legacy interrupts to the Application Layer as
follows:
• int_status[0]: interrupt signal A
• int_status[1]: interrupt signal B
• int_status[2]: interrupt signal C
• int_status[3]: interrupt signal D
ko_cpl_spc_data[11:0]
Output
The Application Layer can use this signal to build circuitry to
prevent RX buffer overflow for completion data. Endpoints must
advertise infinite space for completion data; however, RX buffer
space is finite.
ko_cpl_spc_data
is a static signal that reflects the
total number of 16 byte completion data units that can be stored
in the completion RX buffer.
(3)
Altera does not rigorously test or verify debug signals. Only use debug signals to observe behavior. Do
not use debug signals to drive custom logic.
UG-01097_avmm
2014.12.15
Reset
4-11
64- or 128-Bit Avalon-MM Interface to the Application Layer
Altera Corporation