Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual
Page 93
Byte Offset
Register
Dir
Description
14'h3C28
cfg_msi_addr_hi[63:32]
O
cfg_msi_add[63:32]
is the MSI upper message
address.
14'h3C2C
cfg_io_bas[19:0]
O
The IO base register of the Type1 Configuration
Space. This register is only available in Root Port
mode.
14'h3C30
cfg_io_lim[19:0]
O
The IO limit register of the Type1 Configuration
Space. This register is only available in Root Port
mode.
14'h3C34
cfg_np_bas[11:0]
O
The non-prefetchable memory base register of the
Type1 Configuration Space. This register is only
available in Root Port mode.
14'h3C38
cfg_np_lim[11:0]
O
The non-prefetchable memory limit register of the
Type1 Configuration Space. This register is only
available in Root Port mode.
14'h3C3C
cfg_pr_bas_low[31:0]
O
The lower 32 bits of the prefetchable base register of
the Type1 Configuration Space. This register is only
available in Root Port mode.
14'h3C40
cfg_pr_bas_hi[43:32]
O
The upper 12 bits of the prefetchable base registers
of the Type1 Configuration Space. This register is
only available in Root Port mode.
14'h3C44
cfg_pr_lim_low[31:0]
O
The lower 32 bits of the prefetchable limit registers
of the Type1 Configuration Space. Available in Root
Port mode.
14'h3C48
cfg_pr_lim_hi[43:32]
O
The upper 12 bits of the prefetchable limit registers
of the Type1 Configuration Space. Available in Root
Port mode.
14'h3C4C
cfg_pmcsr[31:0]
O
cfg_pmcsr[31:16]
is Power Management Control
and
cfg_pmcsr[15:0]
is the Power Management
Status register.
14'h3C50
cfg_msixcsr[15:0]
O
MSI-X message control register.
14'h3C54
cfg_msicsr[15:0]
O
MSI message control.
5-24
Control Register Access (CRA) Avalon-MM Slave Port
UG-01097_avmm
2014.12.15
Altera Corporation
Registers