Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual
Page 16
The driver performs the following transactions with status of the transactions displayed in the ModelSim
simulation message window:
1. Various configuration accesses to the Avalon-MM Stratix V Hard IP for PCI Express in your system
after the link is initialized
2. Setup of the Address Translation Table for requests that are coming from the DMA component
3. Setup of the DMA controller to read 512 Bytes of data from the Transaction Layer Direct BFM shared
memory
4. Setup of the DMA controller to write the same data back to the Transaction Layer Direct BFM shared
memory
5. Data comparison and report of any mismatch
The following example shows the transcript from a successful simulation run.
Example 2-1: Transcript from ModelSim Simulation of Gen2 x4 Endpoint
# 464 ns Completed initial configuration of Root Port.
# INFO: 2657 ns EP LTSSM State: DETECT.ACTIVE
# INFO: 3661 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 6049 ns EP LTSSM State: POLLING.ACTIVE
# INFO: 6909 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 9037 ns RP LTSSM State: POLLING.CONFIG
# INFO: 9441 ns EP LTSSM State: POLLING.CONFIG
# INFO: 10657 ns EP LTSSM State:CONFIG.LINKWIDTH.START
# INFO: 10829 ns RP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 11713 ns EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
# INFO: 12253 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
# INFO: 12573 ns RP LTSSM State: CONFIG.LANENUM.WAIT
# INFO: 13505 ns EP LTSSM State: CONFIG.LANENUM.WAIT
# INFO: 13825 ns EP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 13853 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 14173 ns RP LTSSM State: CONFIG.COMPLETE
# INFO: 14721 ns EP LTSSM State: CONFIG.COMPLETE
# INFO: 16001 ns EP LTSSM State: CONFIG.IDLE
# INFO: 16093 ns RP LTSSM State: CONFIG.IDLE
# INFO: 16285 ns RP LTSSM State: L0
# INFO: 16545 ns EP LTSSM State: L0
# INFO: 19112 ns Configuring Bus 001, Device 001, Function 00
# INFO: 19112 ns EP Read Only Configuration Registers:
# INFO: 19112 ns Vendor ID: 0000
# INFO: 19112 ns Device ID: 0001
# INFO: 19112 ns Revision ID: 01
# INFO: 19112 ns Class Code: 000000
# INFO: 19112 ns Subsystem Vendor ID: 0000
# INFO: 19112 ns Subsystem ID: 0000
# INFO: 19112 ns Interrupt Pin: INTA used
# INFO: 20584 ns PCI MSI Capability Register:
# INFO: 20584 ns 64-Bit Address Capable: Supported
# INFO: 20584 ns Messages Requested: 4
# INFO: 28136 ns EP PCI Express Link Status Register (1041):
# INFO: 28136 ns Negotiated Link Width: x4
# INFO: 28136 ns Slot Clock Config: System Reference Clock Used
# INFO: 29685 ns RP LTSSM State: RECOVERY.RCVRLOCK
# INFO: 30561 ns EP LTSSM State: RECOVERY.RCVRLOCK
# INFO: 31297 ns EP LTSSM State: RECOVERY.RCVRCFG
# INFO: 31381 ns RP LTSSM State: RECOVERY.RCVRCFG
# INFO: 32661 ns RP LTSSM State: RECOVERY.IDLE
# INFO: 32961 ns EP LTSSM State: RECOVERY.IDLE
# INFO: 33153 ns EP LTSSM State: L0
# INFO: 33237 ns RP LTSSM State: L0
# INFO: 34696 ns Current Link Speed: 2.5GT/s INFO: 34696 ns
2-4
Generating the Example Design
UG-01097_avmm
2014.12.15
Altera Corporation
Getting Started with the Avalon‑MM Stratix V Hard IP for PCI Express