Altera Stratix V Avalon-MM Interface for PCIe Solutions - Manual (Page 21)

Parameter Settings
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2014.12.15
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Stratix V and Arria V GZ Avalon-MM System Settings
Table 3-1: System Settings for PCI Express
Parameter Value Description
Number of Lanes x1, x2, x4, x8 Specifies the maximum number of lanes supported.
Lane Rate Gen1 (2.5 Gbps)
Gen2 (2.5/5.0 Gbps)
Gen3 (2.5/5.0/8.0
Gbps)
Specifies the maximum data rate at which the link can operate.
Port type Native Endpoint
Root Port
Specifies the port type. Altera recommends Native Endpoint
for all new Endpoint designs. Select Legacy Endpoint only
when you require I/O transaction support for compatibility.
The Endpoint stores parameters in the Type 0 Configuration
Space. The Root Port stores parameters in the Type 1 Configu‐
ration Space.
RX Buffer credit
allocation -
performance for
received requests
Minimum
Low
Balanced
Determines the allocation of posted header credits, posted
data credits, non-posted header credits, completion header
credits, and completion data credits in the 16 KByte RX buffer.
The 5 settings allow you to adjust the credit allocation to
optimize your system. The credit allocation for the selected
setting displays in the message pane.
Refer to the Throughput Optimization chapter for more
information about optimizing performance. The Flow Control
chapter explains how the RX credit allocation and the
Maximum payload RX Buffer credit allocation and the
Maximum payload size that you choose affect the allocation
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