Altera Stratix V Avalon-MM Interface for PCIe Solutions - Manual (Page 62)

Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
Figure 4-10: Arria V GZ and Stratix V GX/GT/GS Gen1 and Gen2 Channel Placement Using the CMU PLL
In the following figures the channels shaded in blue provide the transmit CMU PLL generating the high-
speed serial clock.
Ch5
Ch3
Ch2
Ch1
Ch0 ATX PLL0
CMU PLL ATX PLL1
PCIe Hard IP
Ch0
Ch1
Ch5
Ch3
Ch2
Ch1
Ch0
ATX PLL0
CMU PLL
PCIe Hard IP
ATX PLL1
Ch0
Ch1
Ch2
Ch3
Ch5
Ch3
Ch2
Ch1
Ch0
ATX PLL0
CMU PLL
ATX PLL1
Ch0
Ch1
Ch2
Ch3
Ch11
Ch9
Ch8
Ch7
Ch6
Ch10
PCIe Hard IP
Ch5
Ch6
Ch7
Ch4
Ch5
Ch3
Ch2
CMU PLL
Ch0
ATX PLL0
Ch4 ATX PLL1
PCIe Hard IP
x1
x8
x2
x4
Ch0
UG-01097_avmm
2014.12.15
Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices 4-29
64- or 128-Bit Avalon-MM Interface to the Application Layer Altera Corporation
Send Feedback