Altera Stratix V Avalon-MM Interface for PCIe Solutions - Manual (Page 9)

PCIe Link
PCIe Hard IP
RP
Switch
PCIe
Hard IP
RP
User Application
Logic
PCIe Hard IP
EP
PCIe Link PCIe Link
User Application
Logic
Altera FPGA Hard IP for PCI Express
Altera FPGA with Hard IP for PCI Express
Active Serial or
Active Quad
Device Configuration
Configuration via Protocol (CvP)
using the PCI Express Link
Serial or
Quad Flash
USB
Download
cable
PCIe
Hard IP
EP
User
Application
Logic
Altera FPGA with Hard IP for PCI Express
Config
Control
CVP
USB
Host CPU
PCIe
Related Information
Configuration via Protocol (CvP)Implementation in Altera FPGAs User Guide
Example Designs
The following Qsys example designs are available for the Avalon-MM Stratix V Hard IP for PCI Express
IP Core. You can download them from the /ip/altera/altera_pcie/altera_pcie___hip_avmm/
example_designs directory:
• ep_g1x1.qsys
• ep_g1x4.qsys
• ep_g1x8.qsys
• ep_g2x1.qsys
• ep_g2x4.qsys
• ep_g2x8.qsys
Related Information
Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express on page 2-1
1-8 Example Designs
UG-01097_avmm
2014.12.15
Altera Corporation Datasheet
Send Feedback