Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual
Page 42
Table 4-5: Reset Signals
Signal
Direction
Description
npor
Input
Active low reset signal. In the Altera hardware example designs,
npor
is the
OR
of
pin_perst
and
local_rstn
coming from the
software Application Layer. If you do not drive a soft reset signal
from the Application Layer, this signal must be derived from
pin_perst
. You cannot disable this signal. Resets the entire IP
Core and transceiver. Asynchronous.
In systems that use the hard reset controller, this signal is edge,
not level sensitive; consequently, you cannot use a low value on
this signal to hold custom logic in reset. For more information
about the hard and soft reset controllers, refer to Reset.
nreset_status
Output
Active low reset signal. It is derived from
npor
or
pin_perstn
.
You can use this signal to reset the Application Layer.
pin_perst
Input
Active low reset from the PCIe reset pin of the device.
pin_perst
resets the datapath and control registers. Configuration via
Protocol (CvP) requires this signal. For more information about
CvP refer to Configuration via Protocol (CvP).
Stratix V devices can have up to 4 instances of the Hard IP for
PCI Express. Each instance has its own
pin_perst
signal. You
must connect the
pin_perst
of each Hard IP instance to the
corresponding
nPERST
pin of the device. These pins have the
following locations:
•
NPERSTL0
: bottom left Hard IP and CvP blocks
•
NPERSTL1
: top left Hard IP block
•
NPERSTR0
: bottom right Hard IP block
•
NPERSTR1
: top right Hard IP block
For example, if you are using the Hard IP instance in the bottom
left corner of the device, you must connect
pin_perst
to
NPERSL0
.
For maximum use of the Stratix V device, Altera recommends
that you use the bottom left Hard IP first. This is the only
location that supports CvP over a PCIe link. If your design does
not require CvP, you may select other Hard IP blocks.
Refer to the appropriate device pinout for correct pin assignment
for more detailed information about these pins. The PCI Express
Card Electromechanical Specification 2.0 specifies this pin
requires 3.3 V. You can drive this 3.3V signal to the
nPERST*
UG-01097_avmm
2014.12.15
Reset
4-9
64- or 128-Bit Avalon-MM Interface to the Application Layer
Altera Corporation