Altera Stratix V Avalon-MM Interface for PCIe Solutions - Manual (Page 180)

Date Version Changes Made
• For Stratix V and Arria V GZ devices, corrected channel
placement diagrams for x8. Both Gen3 Channel Placement Using
the CMU and ATX PLLs and Gen1 and Gen2 Channel Placement
Using the ATX PLL show the ATX PLL1 in bank 1 being used.
However, ATX PLL 1 in bank 0 is actually used.
• Updated Power Supply Voltage Requirements table.
• For Arria 10 devices, updated Physical Placement of the Arria 10
Hard IP for PCIe IP and Channels to show GT devices instead of
GX devices.
2013.12.20 13.1 Made the following changes:
• Divided user guide into 3 separate documents by interface type.
• Added Design Implementation chapter.
• In the Debugging chapter, removed section explaining how to turn
off the scrambler for Gen3 because it does not work.
• In the Debugging chapter, corrected filename that you must
change to reduce counter values in simulation.
• In Getting Started with the Avalon-MM Hard IP for PCI Express
chapter, corrected connects for the Transceiver Reconfiguration
Controller IP Core reset signal, alt_xcvr_reconfig_0
mgmt_rst_
reset
. This reset input connects to clk_0
clk_reset
.
• In Transaction Layer Routing Rules and Programming Model for
Avalon-MM Root Port added the fact that Type 0 Configuration
Requests sent to the Root Port are not filtered by the device
number. Application Layer software must filter out requests for
device number greater than 0.
• Added illustration showing the location of the Hard IP Cores in
the Stratix V devices.
• Added limitation for
rxm_irq_[:0]
when interrupts are
received on consecutive cycles.
• Corrected description of
cfg_prm_cmr
. It is the Base/Primary
Command register for the PCI Configuration Space.
• Revised channel placement illustrations.
C-4 Revision History for the Avalon-MM Interface
UG-01097_avmm
2014.12.15
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