Altera Stratix V Avalon-MM Interface for PCIe Solutions - Manual (Page 158)

SDC Constraints for the Qsys Example Design
The .sdc file includes constraints for the Transceiver Reconfiguration Controller IP Core which is
included in the Qsys example designs. You may need to change the frequency and actual clock pin name
to match your design. The .sdc file also specifies some false timing paths for Transceiver Reconfiguration
Controller and Transceiver PHY Reset Controller IP Cores. Be sure to include these constraints in
your .sdc file.
12-4 SDC Timing Constraints
UG-01097_avmm
2014.12.15
Altera Corporation Design Implementation
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