Altera Stratix V Avalon-MM Interface for PCIe Solutions - Manual (Page 126)

Figure 9-1: Stratix V Hard IP for PCI Express Using the Avalon-MM Interface
Clock
Domain
Crossing
(CDC)
Data
Link
Layer
(DLL)
Transaction
Layer (TL)
PHYMAC
Hard IP for PCI Express
Avalon-MM
TX Master
Avalon-MM
TX Slave
Avalon-MM
CRA Slave
(optional)
Reconfiguration
PIPE
Application
Layer
Clock & Reset
Selection
Configuration
Block
Configuration
Space
PCS PMA
Physical Layer
(Transceivers)
Configuration via PCIe Link
RX Buffer
PHY IP Core for
PCI Express (PIPE)
Avalon-MM
Bridge
Table 9-1: Application Layer Clock Frequencies
Lanes Gen1 Gen2 Gen3
×1 125 MHz @ 64 bits or
62.5 MHz @ 64 bits
125 MHz @ 64 bits 125 MHz @64 bits
×2 125 MHz @ 64 bits 125 MHz @ 128 bits 250 MHz @ 64 bits or
125 MHz @ 128 bits
×4 125 MHz @ 64 bits 250 MHz @ 64 bits or
125 MHz @ 128 bits 250 MHz @ 128 bits or
125 MHz @ 256 bits
×8 250 MHz @ 64 bits or
125 MHz @ 128 bits
250 MHz @ 128 bits or
125 MHz @ 256 bits 250 MHz @ 256 bits
Related Information
PCI Express Base Specification 2.1 or 3.0
9-2 IP Core Architecture
UG-01097_avmm
2014.12.15
Altera Corporation IP Core Architecture
Send Feedback