Hard ip status extension – Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual
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Hard IP Status Extension
Table 4-10: Hard IP Status Extension Signals
This optional bus adds signals that are useful for debugging to the top-level variant, including:
• The most important native Avalon-ST RX signals
• The Configuration Space signals
• The BAR
• The ECC error
• The signal indicating that the
pld_clk
is in use
Signal
Direction
Description
pld_clk_inuse
Output
When asserted, indicates that the Hard IP Transaction Layer is
using the
pld_clk
as its clock and is ready for operation with the
Application Layer. For reliable operation, hold the Application
Layer in reset until
pld_clk_inuse
is asserted.
pme_to_sr
Output
Power management turn off status register.
Root Port—This signal is asserted for 1 clock cycle when the Root
Port receives the
pme_turn_off
acknowledge message.
Endpoint—This signal is asserted for 1 cycle when the Endpoint
receives the
PME_turn_off
message from the Root Port.
UG-01097_avmm
2014.12.15
Hard IP Status Extension
4-17
64- or 128-Bit Avalon-MM Interface to the Application Layer
Altera Corporation