Altera Arria V Avalon-ST User Manual
Page 94
Signal
Direction
Description
sim_pipe_rate[1:0]
Output
The 2-bit encodings have the following meanings:
• 2’b00: Gen1 rate (2.5 Gbps)
• 2’b01: Gen2 rate (5.0 Gbps)
• 2’b1X: Gen3 rate (8.0 Gbps)
sim_pipe_pclk_in
Input
This clock is used for PIPE simulation only, and is derived from
the
refclk
. It is the PIPE interface clock used for PIPE mode
simulation.
txswing0
Output
When asserted, indicates full swing for the transmitter voltage.
When deasserted indicates half swing.
tx_margin0[2:0]
Output
Transmit V
OD
margin selection. The value for this signal is based
on the value from the
Link Control 2
Register
. Available for
simulation only.
Notes:
1. These signals are for simulation only. For Quartus II software compilation, these pipe signals can be
left floating.
2014.12.15
PIPE Interface Signals
4-57
Interfaces and Signal Descriptions
Altera Corporation