Altera Arria V Avalon-ST - Manual (Page 19)

Complete the following steps to create your Quartus II project:
1. Click the New Project Wizard icon.
2. Click Next in the New Project Wizard: Introduction (The introduction does not appear if you
previously turned it off)
3. On the Directory, Name, Top-Level Entity page, enter the following information:
a. The working directory shown is correct. You do not have to change it.
b. For the project name, browse to the synthesis directory that includes your Qsys project,
/pcie_de_gen1_x4_ast64/synthesis . Select your variant name, pcie_de_gen1_x4_ast64.v .
Then, click Open.
c. If the top-level design entity and Qsys system names are identical, the Quartus II software treats the
Qsys system as the top-level design entity.
4. Click Next to display the Add Files page.
5. Complete the following steps to add the Quartus II IP File (.qip)to the project:
a. Click the browse button. The Select File dialog box appears.
b. In the Files of type list, select IP Variation Files (*.qip).
c. Browse to the
/pcie_de_gen1_x4_ast64/synthesis directory.
d. Click pcie_de_gen1_x4_ast64.qip and then click Open.
e. On the Add Files page, click Add, then click OK.
6. Click Next to display the Device page.
7. On the Family & Device Settings page, choose the following target device family and options:
a. In the Family list, select Arria V (GT/GX/ST/SX).
b. In the Devices list, select Arria V GX Extended Features..
c. In the Available Devices list, select 5AGXFB3H6F35C6.
8. Click Next to close this page and display the EDA Tool Settings page.
9. From the Simulation list, select ModelSim ® . From the Format list, select the HDL language you
intend to use for simulation.
10.Click Next to display the Summary page.
11.Check the Summary page to ensure that you have entered all the information correctly.
12.Click Finish to create the Quartus II project.
13.Add the Synopsys Design Constraint (SDC) commands shown in the following example to the
top-level design file for your Quartus II project.
14.To compile your design using the Quartus II software, on the Processing menu, click Start Compila‐
tion. The Quartus II software then performs all the steps necessary to compile your design.
15.After compilation, expand the TimeQuest Timing Analyzer folder in the Compilation Report. Note
whether the timing constraints are achieved in the Compilation Report.
16.If your design does not initially meet the timing constraints, you can find the optimal Fitter settings for
your design by using the Design Space Explorer. To use the Design Space Explorer, click Launch
Design Space Explorer on the tools menu.
Example 2-1: Synopsys Design Constraints
create_clock -period “100 MHz” -name {refclk_pci_express}{*refclk_*}
derive_pll_clocks
derive_clock_uncertainty
2-6 Compiling the Design in the Quartus II Software
2014.12.15
Altera Corporation Getting Started with the Arria V Hard IP for PCI Express
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