Altera Arria V Avalon-ST - Manual (Page 83)

Signal Direction Description
pm_data[9:0] Input Power Management Data.
This bus indicates power consumption of the component. This
bus can only be implemented if all three bits of
AUX_power
(part
of the Power Management Capabilities structure) are set to 0.
This bus includes the following bits:
•
pm_data[9:2]
: Data Register: This register maintains a value
associated with the power consumed by the component.
(Refer to the example below)
•
pm_data[1:0]
: Data Scale: This register maintains the scale
used to find the power consumed by a particular component
and can include the following values:
• 2b’00: unknown
• 2b’01: 0.1 ×
• 2b’10: 0.01 ×
• 2b’11: 0.001 ×
For example, the two registers might have the following values:
•
pm_data[9:2]
: b’1110010 = 114
•
pm_data[1:0]
: b’10, which encodes a factor of 0.01
To find the maximum power consumed by this component,
multiply the data value by the data Scale (114 × .01 = 1.14). 1.14
watts is the maximum power allocated to this component in the
power state selected by the
data_select
field.
pm_auxpwr Input Power Management Auxiliary Power: This signal can be tied to 0
because the L2 power state is not supported.
Figure 4-33: Layout of Power Management Capabilities Register
data_select data_scale PM_state PME_EN PME_status reserved
15 0 1 16 23 8 2 7 9 12 13 14 24 31
reserved
data
register
Table 4-18: Power Management Capabilities Register Field Descriptions
Bits Field Description
[31:24] Data register This field indicates in which power states a function can assert
the
PME# message
.
[23:16] reserved —
4-46 Power Management Signals
2014.12.15
Altera Corporation Interfaces and Signal Descriptions
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