Altera Arria V Avalon-ST - Manual (Page 162)

You can also enter these commands at the Quartus II Tcl Console. For example, the following command
sets the
XCVR_VCCR_VCCT_VOLTAGE
to 1.0 V for the pin specified:
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V to “pin”
Related Information
• Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines
• Arria V Device Datasheet
Making Pin Assignments
Before running Quartus II compilation, use the Pin Planner to assign I/O standards to the pins of the
device. Complete the following steps to bring up the Pin Planner and assign the 1.5-V pseudo-current
mode logic (PCML) I/O standard to the serial data input and output pins:
1. On the Quartus II Assignments menu, select Pin Planner. The Pin Planner appears.
2. In the Node Name column, locate the PCIe serial data pins.
3. In the I/O Standard column, double-click the right-hand corner of the box to bring up a list of
available I/O standards.
4. Select 1.5 V PCML I/O standard.
Note: The IP core automatically assigns other required PMA analog settings, including 100 ohm internal
termination.
Recommended Reset Sequence to Avoid Link Training Issues
1. Wait until the FPGA is configured as indicated by the assertion of
CONFIG_DONE
from the FPGA block
controller.
2. Deassert the
mgmt_rst_reset
input to the Transceiver Reconfiguration Controller IP Core.
3. Wait for
tx_cal_busy
and
rx_cal_busy
SERDES outputs to be deasserted.
4. Deassert
pin_perstn
to take the Hard IP for PCIe out of reset. For plug-in cards, the minimum
assertion time for
pin_perstn
is 100 ms. Embedded systems do not have a minimum assertion time
for
pin_perstn
.
5. Wait for the
reset_status
output to be deasserted
6. Deassert the reset output to the Application Layer.
Related Information
Reset Sequence for Hard IP for PCI Express IP Core and Application Layer on page 6-3
12-2 Making Pin Assignments
2014.12.15
Altera Corporation Design Implementation
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