Altera Arria V Avalon-ST - Manual (Page 10)

Figure 1-5: Example Design Preset Parameters
• Targeted Device Family
• Lanes
• Lane Rate
• Application Clock Rate
• Port type
• Application Interface
• Tags supported
• Maximum payload size
• Number of functions
The following example designs are available for the Arria V Hard IP for PCI Express. You can download
them from the / ip/altera/altera_pcie/altera_pcie_hip_ast_ec/example_design/ directory:
• pcie_de_gen1_x2_ast64.qsys
• pcie_de_gen1_x4_ast64.qsys
• pcie_de_gen1_x8_ast128.qsys
• pcie_de_rp_gen1_x4_ast64.qsys
• pcie_de_rp_gen1_x8_ast128.qsys
Click on the link below to get started with the example design provided in this user guide.
Related Information
Getting Started with the Arria V Hard IP for PCI Express on page 2-1
Debug Features
Debug features allow observation and control of the Hard IP for faster debugging of system-level
problems.
2014.12.15
Debug Features 1-9
Datasheet Altera Corporation
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