Altera Arria V Avalon-ST User Manual
Page 62
Table 4-6: Reset Signals
Signal
Direction
Description
npor
Input
Active low reset signal. In the Altera hardware example designs,
npor
is the
OR
of
pin_perst
and
local_rstn
coming from the
software Application Layer. If you do not drive a soft reset signal
from the Application Layer, this signal must be derived from
pin_perst
. You cannot disable this signal. Resets the entire IP
Core and transceiver. Asynchronous.
In systems that use the hard reset controller, this signal is edge,
not level sensitive; consequently, you cannot use a low value on
this signal to hold custom logic in reset. For more information
about the hard and soft reset controllers, refer to the Reset and
Clocks chapter.
reset_status
Output
Active high reset status signal. When asserted, this signal
indicates that the Hard IP clock is in reset. The
reset_status
signal is synchronous to the
pld_clk
clock and is deasserted only
when the
npor
is deasserted and the Hard IP for PCI Express is
not in reset (
reset_status_hip
= 0). You should use
reset_
status
to drive the reset of your application. This reset is used
for the Hard IP for PCI Express IP Core with the Avalon-ST
interface.
pin_perst
Input
Active low reset from the PCIe reset pin of the device.
pin_perst
resets the datapath and control registers. This signal is required
for Configuration via Protocol (CvP). For more information
about CvP refer to Configuration via Protocol (CvP).
Arria V have 1 or 2 instances of the Hard IP for PCI Express.
Each instance has its own
pin_perst
signal. You must connect
the
pin_perst
of each Hard IP instance to the corresponding
nPERST
pin of the device. These pins have the following locations:
•
nPERSTL0
: bottom left Hard IP and CvP blocks
•
nPERSTL1
: top left Hard IP block
For example, if you are using the Hard IP instance in the bottom
left corner of the device, you must connect
pin_perst
to
nPERSL0
.
For maximum use of the Arria V device, Altera recommends that
you use the bottom left Hard IP first. This is the only location
that supports CvP over a PCIe link.
Refer to the appropriate device pinout for correct pin assignment
for more detailed information about these pins. The PCI Express
Card Electromechanical Specification 2.0 specifies this pin
requires 3.3 V. You can drive this 3.3V signal to the
nPERST*
2014.12.15
Reset Signals
4-25
Interfaces and Signal Descriptions
Altera Corporation