Altera Arria V Avalon-ST - Manual (Page 193)

The top-level of the testbench instantiates the following key files:
• altlpcietb_bfm_top_ep.v— this is the Endpoint BFM. This file also instantiates the SERDES and PIPE
interface.
• altpcietb_pipe_phy.v—used to simulate the PIPE interface.
• altp cietb_bfm_ep_example_chaining_pipen1b.v—the top-level of the Root Port design example that
you use for simulation. This module instantiates the Root Port variation, .v, and the
Root Port application altpcietb_bfm_vc_intf _ . This module provides both PIPE
and serial interfaces for the simulation environment. This module has two debug ports named
test_out_icm
_(which is the
test_out
signal from the Hard IP) and
test_in
which allows you to
monitor and control internal states of the Hard IP variation.
• altpcietb_bfm_vc_intf_ast.v—a wrapper module which instantiates either altpcietb_vc_intf_64 or
altpcietb_vc_intf_ based on the type of Avalon-ST interface that is generated.
• altpcietb_vc_intf_ _ .v—provide the interface between the Arria V Hard IP for
PCI Express variant and the Root Port BFM tasks. They provide the same function as the
altpcietb_bfm_vc_intf.v module, transmitting requests and handling completions. Refer to the Root
Port BFM for a full description of this function. This version uses Avalon-ST signalling with either a
64- or 128-bit data bus interface.
• altpcierd_tl_cfg_sample.v—accesses Configuration Space signals from the variant. Refer to the
Chaining DMA Design Examples for a description of this module.
Files in subdirectory /testbench/simulation/submodules:
• altpcietb_bfm_ep_example_chaining_pipen1b.v—the simulation model for the chaining DMA
Endpoint.
• altpcietb_bfm_driver_rp.v–this file contains the functions to implement the shared memory space,
PCI Express reads and writes, initialize the Configuration Space registers, log and display simulation
messages, and define global constants.
Related Information
• Test Driver Module on page 16-16
• Chaining DMA Design Examples on page 16-4
Root Port BFM
The basic Root Port BFM provides Verilog HDL task-based interface for requesting transactions that are
issued to the PCI Express link. The Root Port BFM also handles requests received from the PCI Express
link. The following figure provides an overview of the Root Port BFM.
2014.12.15
Root Port BFM 16-23
Testbench and Design Example Altera Corporation
Send Feedback