Altera Arria V Avalon-ST - Manual (Page 8)

Figure 1-3: PCI Express Application with an Endpoint Using the Multi-Function Capability
The following figure shows a PCI Express link between two Altera FPGAs. One is configured as a Root
Port and the other as a multi-function Endpoint. The FPGA serves as a custom I/O hub for the host CPU.
In the Arria V FPGA, each peripheral is treated as a function with its own set of Configuration Space
registers. Eight multiplexed functions operate using a single PCI Express link.
Arria V or Cyclone V FPGA
PCIe Hard
IP Multi-
Function
EP
CAN GbE ATA PCI
Altera FPGA
PCIe
Hard IP
RP
Host
CPU
Memory
Controller
Peripheral
Controller
Peripheral
Controller
USB SPI GPIO I2C
PCI Express Link
Figure 1-4: PCI Express Application Using Configuration via Protocol
The Arria V design below includes the following components:
• A Root Port that connects directly to a second FPGA that includes an Endpoint.
• Two Endpoints that connect to a PCIe switch.
• A host CPU that implements CvP using the PCI Express link connects through the switch. For more
information about configuration over a PCI Express link below.
2014.12.15
Configurations 1-7
Datasheet Altera Corporation
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