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Hard ip reconfiguration – Altera Arria V Avalon-ST User Manual

Page 167

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Hard IP Reconfiguration

14

2014.12.15

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The Arria V Hard IP for PCI Express reconfiguration block allows you to dynamically change the value of

configuration registers that are read-only. You access this block using its Avalon-MM slave interface. You

must enable this optional functionality by turning on Enable Hard IP Reconfiguration in the parameter

editor. For a complete description of the signals in this interface, refer to Hard IP Reconfiguration

Interface.
The Hard IP reconfiguration block provides access to read-only configuration registers, including

Configuration Space, Link Configuration, MSI and MSI-X capabilities, Power Management, and

Advanced Error Reporting (AER). This interface does not support simulation.
The procedure to dynamically reprogram these registers includes the following three steps:
1. Bring down the PCI Express link by asserting the

hip_reconfig_rst_n

reset signal, if the link is

already up. (Reconfiguration can occur before the link has been established.)

2. Reprogram configuration registers using the Avalon-MM slave Hard IP reconfiguration interface.

3. Release the

npor

reset signal.

Note: You can use the LMI interface to change the values of configuration registers that are read/write at

run time. For more information about the LMI interface, refer to LMI Signals.

Contact your Altera representative for descriptions of the read-only, reconfigurable registers.

Related Information

LMI Signals

on page 4-42

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