Altera Arria V Avalon-ST - Manual (Page 231)

Possible Causes Symptoms and Root Causes Workarounds and Solutions
Flow control credit
overflows
Determine if the credit field
associated with the current TLP
type in the
tx_cred
bus is less
than the requested credit value.
When insufficient credits are
available, the core waits for the
link partner to release the
correct credit type. Sufficient
credits may be unavailable if the
link partner increments credits
more than expected, creating a
situation where the Arria V
Hard IP for PCI Express IP Core
credit calculation is out-of-sink
with its link partner.
Add logic to detect conditions where the
tx_st_
ready
signal remains deasserted for more than
100 cycles. Set post-triggering conditions to
check the value of the
tx_cred*
and
tx_st_*
interfaces. Add a FIFO status signal to
determine if the TXFIFO is full.
Malformed TLP is
transmitted
Refer to the error log file to find
the last good packet transmitted
on the link. Correlate this packet
with TLP sent on Avalon-ST
interface. Determine if the last
TLP sent has any of the
following errors:
• The actual payload sent does
not match the length field.
• The byte enable signals
violate rules for byte enables
as specified in the Avalon
Interface Specifications.
• The format and type fields
are incorrectly specified.
• TD field is asserted,
indicating the presence of a
TLP digest (ECRC), but the
ECRC dword is not present
at the end of TLP.
• The payload crosses a 4KByte
boundary.
Revise the Application Layer logic to correct the
error condition.
2014.12.15
Debugging Link Failure in L0 Due To Deassertion of tx_st_ready 17-3
Debugging Altera Corporation
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