Altera Arria V Avalon-ST - Manual (Page 135)

Figure 9-1: Arria V Hard IP for PCI Express Using the Avalon-ST Interface
Clock
Domain
Crossing
(CDC)
Data
Link
Layer
(DLL)
Transaction Layer (TL)
PHYMAC
Hard IP for PCI Express
Avalon-ST TX
Avalon-ST RX
Side Band
Local
Management
Interface (LMI)
&
Reconfiguration
PIPE
Application
Layer
Clock & Reset
Selection
Configuration
Block
Configuration
Space
PCS PMA
Physical Layer
(Transceivers)
Configuration via PCIe Link
RX Buffer
PHY IP Core for
PCI Express (PIPE)
Table 9-1: Application Layer Clock Frequencies
Lanes Gen1 Gen2
×1 125 MHz @ 64 bits or
62.5 MHz @ 64 bits
125 MHz @ 64 bits
×2 125 MHz @ 64 bits 125 MHz @ 64 bits
×4 125 MHz @ 64 bits 125 MHz @ 128 bits
×8 125 MHz @ 128 bits
N/A
The following interfaces provide access to the Application Layer’s Configuration Space Registers:
• The LMI interface
• The Avalon-MM PCIe reconfiguration interface, which can access any read-only Configuration Space
Register
• In Root Port mode, you can also access the Configuration Space Registers with a Configuration TLP
using the Avalon-ST interface. A Type 0 Configuration TLP is used to access the Root Port configura‐
tion Space Registers, and a Type 1 Configuration TLP is used to access the Configuration Space
Registers of downstream components, typically Endpoints on the other side of the link.
The Hard IP includes dedicated clock domain crossing logic (CDC) between the PHYMAC and Data Link
Layers.
9-2 IP Core Architecture
2014.12.15
Altera Corporation IP Core Architecture
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