Data link layer – Altera Arria V Avalon-ST User Manual
Page 140
The Configuration Space also generates all messages (PME#, INT, error, slot power limit), MSI requests,
and completion packets from configuration requests that flow in the direction of the root complex, except
slot power limit messages, which are generated by a downstream port. All such transactions are
dependent upon the content of the PCI Express Configuration Space as described in the PCI Express Base
Specification.
Related Information
•
Type 0 Configuration Space Registers
•
Data Link Layer
The Data Link Layer is located between the Transaction Layer and the Physical Layer. It maintains packet
integrity and communicates (by DLL packet transmission) at the PCI Express link level (as opposed to
component communication by TLP transmission in the interconnect fabric).
The DLL implements the following functions:
• Link management through the reception and transmission of DLL packets (DLLP), which are used for
the following functions:
• Power management of DLLP reception and transmission
• To transmit and receive
ACK
/
NACK
packets
• Data integrity through generation and checking of CRCs for TLPs and DLLPs
• TLP retransmission in case of
NAK
DLLP reception using the retry buffer
• Management of the retry buffer
• Link retraining requests in case of error through the Link Training and Status State Machine
(LTSSM) of the Physical Layer
2014.12.15
Data Link Layer
9-7
IP Core Architecture
Altera Corporation