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C. additional information, Revision history for the avalon-st interface, Additional information – Altera Arria V Avalon-ST User Manual

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Additional Information

C

2014.12.15

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Revision History for the Avalon-St Interface

Date

Version

Changes Made

2014.12.15

14.1

Made the following changes to the user guide:
• In the figured titled Specifying the Number of Transceiver

Interfaces for Arria V and Cyclone V Devices, removed the

checkmark Calibrate duty cycle during power up. Duty cycle

calibration occurs during Gen1 to Gen2 speed changes.

• Corrected discussion of soft and hard reset controllers. The

hardened reset controller is used for Arria V and Cyclone V

devices.

• Added simulation log file,

altpcie_monitor__dlhip_tlp_file_

log.log

in your simulation directory. Generation of the log file

requires the following simulation file,

altera/altera_pcie/

altera_pcie_a10_hip/altpcie_monitor_a10_dlhip_sim.sv

, that was not

present in earlier releases of the Quartus II software.

• Added statement that the bottom left hard IP block includes the

CvP functionality for flip chip packages. For other package types,

the CvP functionality is in the bottom right block.

• Corrected bit definitions for

CvP Status

register.

• Updated definition of

CVP_NUMCLKS

in the

CvP Mode Control

register.

• Added definitions for

test_in[2]

,

test_in[6]

and

test_in[7]

.

• Corrected Channel Utilization table for x1 instances. Data is

driven on Channel 0. The CMU clock is on Channel 1.

2014.06.30

14.0

Made the following changes to the Arria V Hard IP for PCI Express:
• Increased the size of

lmi_addr

to 15 bits.

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