Altera Arria V Avalon-ST - Manual (Page 125)

Related Information
Correspondence between Configuration Space Registers and the PCIe Specification on page 5-1
Enabling MSI or Legacy Interrupts
The PCI Express Avalon-MM bridge selects either MSI or legacy interrupts automatically based on the
standard interrupt controls in the PCI Express Configuration Space registers. Software can write the
Interrupt Disable
bit, which is bit 10 of the
Command
register (at Configuration Space offset 0x4) to
disable legacy interrupts. Software can write the
MSI Enable
bit, which is bit 0 of the
MSI Control
Status
register in the MSI capability register (bit 16 at configuration space offset 0x50), to enable MSI
interrupts.
Software can only enable one type of interrupt at a time. However, to change the selection of MSI or
legacy interrupts during operation, software must ensure that no interrupt request is dropped. Therefore,
software must first enable the new selection and then disable the old selection. To set up legacy interrupts,
software must first clear the
Interrupt Disable
bit and then clear the
MSI enable
bit. To set up MSI
interrupts, software must first set the
MSI enable
bit and then set the
Interrupt Disable
bit.
Interrupts for Root Ports
In Root Port mode, the Arria V Hard IP for PCI Express receives interrupts through two different
mechanisms:
• MSI—Root Ports receive MSI interrupts through the Avalon-ST RX TLP of type
MWr
. This is a memory
mapped mechanism.
• Legacy—Legacy interrupts are translated into TLPs of type
Message Interrupt
which is sent to the
Application Layer using the
int_status[3:0]
pins.
Normally, the Root Port services rather than sends interrupts; however, in two circumstances the Root
Port can send an interrupt to itself to record error conditions:
• When the AER option is enabled, the
aer_msi_num[4:0]
signal indicates which MSI is being sent to
the root complex when an error is logged in the AER Capability structure. This mechanism is an
alternative to using the
serr_out
signal. The
aer_msi_n um[4:0]
is only used for Root Ports and you
must set it to a constant value. It cannot toggle during operation.
• If the Root Port detects a Power Management Event, the
pex_msi_num[4:0]
signal is used by Power
Management or Hot Plug to determine the offset between the base message interrupt number and the
message interrupt number to send through MSI. The user must set
pex_msi_num[4:0]
to a fixed value.
The
Root Error Status
register reports the status of error messages. The
Root Error Status
register is
part of the PCI Express AER Extended Capability structure. It is located at offset 0x830 of the Configura‐
tion Space registers.
2014.12.15
Enabling MSI or Legacy Interrupts 7-7
Interrupts Altera Corporation
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