Altera Arria V Avalon-ST - Manual (Page 233)

altpcie__hip_ast_hwtcl #( .enable_pipe32_sim_hwtcl ( 1 ),
Using the PIPE Interface for Gen1 and Gen2 Variants
Running the simulation in PIPE mode reduces simulation time and provides greater visibility.
Complete the following steps to simulate using the PIPE interface:
1. Change to your simulation directory,
//testbench/_tb/simulation
2. Open
_tb.v .
3. Search for the string,
serial_sim_hwtcl
. Set the value of this parameter to 0 if it is 1.
4. Save
_tb.v .
Reducing Counter Values for Serial Simulations
You can accelerate simulation by reducing the value of counters whose default values are set for hardware,
not simulation.
Complete the following steps to reduce counter values for simulation:
1. Open
//testbench/_tb/simulation/submodules/altpcie_tbed__hwtcl.v .
2. Search for the string,
test_in
.
3. To reduce the value of several counters, set
test_in[0] = 1
.
4. Save
altpcietb_bfm_top_rp.v
.
Disable the Scrambler for Gen1 and Gen2 Simulations
The encoding scheme implemented by the scrambler applies a binary polynomial to the data stream to
ensure enough data transitions between 0 and 1 to prevent clock drift. The data is decoded at the other
end of the link by running the inverse polynomial.
Complete the following steps to disable the scrambler:
1. Open
//testbench/_tb/simulation/submodules/altpcie_tbed__hwtcl.v .
2. Search for the string,
test_in
.
3. To disable the scrambler, set
test_in[2] = 1
.
4. Save
altpcie_tbed_sv_hwtcl.v .
Changing between the Hard and Soft Reset Controller
The Hard IP for PCI Express includes both hard and soft reset control logic. By default, Gen1 devices use
the Hard Reset Controller. Gen2 devices use the soft reset controller. For variants that use the hard reset
controller, changing to the soft reset controller provides greater visibility.
Complete the following steps to change to the soft reset controller:
1. Open
//testbench/_tb/simulation/submodules/.v
.
2. Search for the string,
hip_hard_reset_hwtcl
.
3. If
hip_hard_reset_hwtcl = 1
, the hard reset controller is active. Set
hip_hard_reset_hwtcl = 0
to
change to the soft reset controller.
4. Save
variant.v .
2014.12.15
Using the PIPE Interface for Gen1 and Gen2 Variants 17-5
Debugging Altera Corporation
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