Altera Arria V Avalon-ST - Manual (Page 7)

Configurations
The Arria V Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stack
comprising the following layers:
• Physical (PHY), including:
• Physical Media Attachment (PMA)
• Physical Coding Sublayer (PCS)
• Media Access Control (MAC)
• Data Link Layer (DL)
• Transaction Layer (TL)
The Hard IP supports all memory, I/O, configuration, and message transactions. It is optimized for Altera
devices. The Application Layer interface is also optimized to achieve maximum effective throughput. You
can customize the Hard IP to meet your design requirements.
Figure 1-2: PCI Express Application with a Single Root Port and Endpoint
The following figure shows a PCI Express link between two Arria V FPGAs. One is configured as a Root
Port and the other as an Endpoint.
Altera FPGA
User Application
Logic
PCIe
Hard IP
RP
PCIe
Hard IP
EP
User Application
Logic PCI Express Link
Altera FPGA
1-6 Configurations
2014.12.15
Altera Corporation Datasheet
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