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Local management interface (lmi interface), Hard ip reconfiguration, Transceiver reconfiguration – Altera Arria V Avalon-ST User Manual

Page 137: Interrupts, Pipe

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Local Management Interface (LMI Interface)

The LMI bus provides access to the PCI Express Configuration Space in the Transaction Layer.

Related Information

LMI Signals

on page 4-42

Hard IP Reconfiguration

The PCI Express reconfiguration bus allows you to dynamically change the

read-only

values stored in

the Configuration Registers.

Related Information

Hard IP Reconfiguration Interface

on page 4-52

Transceiver Reconfiguration

The transceiver reconfiguration interface allows you to dynamically reconfigure the values of analog

settings in the PMA block of the transceiver. Dynamic reconfiguration is necessary to compensate for

process variations.

Related Information

Transceiver PHY IP Reconfiguration

on page 15-1

Interrupts

The Hard IP for PCI Express offers the following interrupt mechanisms:
• Message Signaled Interrupts (MSI)— MSI uses the Transaction Layer's request-acknowledge

handshaking protocol to implement interrupts. The MSI Capability structure is stored in the Configu‐

ration Space and is programmable using Configuration Space accesses.

• MSI-X—The Transaction Layer generates MSI-X messages which are single dword memory writes. In

contrast to the MSI capability structure, which contains all of the control and status information for

the interrupt vectors, the MSI-X Capability structure points to an MSI-X table structure and MSI-X

PBA structure which are stored in memory.

• Legacy interrupts—

app_int_sts_vec[7:0]

controls legacy interrupt generation. When asserted, the

Hard IP to generates an

Assert_INT

message TLP.

Related Information

Interrupts for Endpoints

on page 4-30

Interrupts for Root Ports

on page 4-31

PIPE

The PIPE interface implements the Intel-designed PIPE interface specification. You can use this parallel

interface to speed simulation; however, you cannot use the PIPE interface in actual hardware. The Gen1

and Gen2 simulation models support PIPE and serial simulation.

Related Information

PIPE Interface Signals

on page 4-54

9-4

Local Management Interface (LMI Interface)

2014.12.15

Altera Corporation

IP Core Architecture

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