Altera Arria V Avalon-ST - Manual (Page 51)

Table 4-4: 64- or 128‑Bit Avalon-ST TX Datapath
Signal Direction Description
tx_st_data[-1:0] Input Data for transmission. Transmit data bus. Refer to the following
sections on data alignment for the 64- and 128-bit interfaces for
the mapping of TLP packets to
tx_st_data
and examples of the
timing of this interface. When using a 64-bit Avalon-ST bus, the
width of
tx_st_d ata
is 64. When using a 128-bit Avalon-ST
bus, the width of
tx_st_data
is 128 bits. The Application Layer
must provide a properly formatted TLP on the TX interface. The
mapping of message TLPs is the same as the mapping of Transac‐
tion Layer TLPs with 4 dword headers. The number of data
cycles must be correct for the length and address fields in the
header. Issuing a packet with an incorrect number of data cycles
results in the TX interface hanging and becoming unable to
accept further requests.
= 64 or 128.
tx_st_sop Input Indicates first cycle of a TLP when asserted together with
tx_st_
valid
.
tx_st_eop Input Indicates last cycle of a TLP when asserted together with
tx_st_
valid
.
tx_st_ready
Output Indicates that the Transaction Layer is ready to accept data for
transmission. The core deasserts this signal to throttle the data
stream.
tx_st_ready
may be asserted during reset. The Applica‐
tion Layer should wait at least 2 clock cycles after the reset is
released before issuing packets on the Avalon-ST TX interface.
The
reset_status
signal can also be used to monitor when the
IP core has come out of reset.
If
tx_st_ready
is asserted by the Transaction Layer on cycle
, then
+ readyLatency>
is a ready cycle, during which
the Application Layer may assert
valid
and transfer data.
When
tx_st_ready
,
tx_st_valid
and
tx_st_data
are
registered (the typical case), Altera recommends a
readyLa-
tency
of 2 cycles to facilitate timing closure; however, a
readyLatency
of 1 cycle is possible. If no other delays are added
to the read-valid latency, the resulting delay corresponds to a
readyLatency
of 2.
4-14 Avalon-ST TX Interface
2014.12.15
Altera Corporation Interfaces and Signal Descriptions
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