Altera Arria V Avalon-ST - Manual (Page 70)

Signal Directi
on
Description
•
cpl_err[4]
: Unsupported Request (UR) error for posted TLP.
The Application Layer asserts this signal to treat a posted request
as an Unsupported Request. The Hard IP automatically sets the
error status bits in the Configuration Space register and sends
error messages in accordance with the PCI Express Base Specifica‐
tion. Many cases of Unsupported Requests are detected and
reported internally by the Transaction Layer. For a list of these
cases, refer to Transaction Layer Errors.
•
cpl_err[5]
: Unsupported Request error for non-posted TLP. The
Application Layer asserts this signal to respond to a non-posted
request with an Request (UR) completion. In this case, the
Application Layer sends a completion packet with the
Unsupported Request status back to the requestor, and asserts this
error signal. The Hard IP automatically sets the error status bits in
the Configuration Space Register and sends error messages in
accordance with the PCI Express Base Specification. Many cases of
Unsupported Requests are detected and reported internally by the
Transaction Layer. For a list of these cases, refer to Transaction
Layer Errors.
•
cpl_err[6]
: Log header. If header logging is required, this bit
must be set in the every cycle in which any of
cpl_err[2]
,
cpl_
err[3]
,
cpl_err[4]
, or
cpl_err[5]
is set. The Application Layer
presents the header to the Hard IP by writing the following values
to the following 4 registers using LMI before asserting
cpl_
err[6]
:. The Application Layer presents the header to the Hard IP
by writing the following values to the following 4 registers using
LMI before asserting
cpl_err[6]:
• lmi_addr: 12'h81C,
lmi_din
:
err_desc_func0[127:96]
• lmi_addr: 12'h820,
lmi_din
:
err_desc_func0[95:64]
• lmi_addr: 12'h824,
lmi_din
:
err_desc_func0[63:32]
• lmi_addr: 12'h828,
lmi_din
:
err_desc_func0[31:0]
cpl_pending[7:0] Input Completion pending. The Application Layer must assert this signal
when a master block is waiting for completion, for example, when a
transaction is pending. This is a level sensitive input. A bit is provided
for each function, where bit 0 corresponds to function 0, and so on.
cpl_err_func[2:0] Specifies which function is requesting the
cpl_err
. Must be asserted
when
cpl_err
asserts. Due to clock-domain synchronization
circuitry,
cpl_err
is limited to at most 1 assertion every 8
pld_clk
cycles. Whenever
cpl_err
is asserted,
cpl_err_func[2:0]
should be
updated in the same cycle.
2014.12.15
Completion Side Band Signals 4-33
Interfaces and Signal Descriptions Altera Corporation
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