Altera Arria V Avalon-ST - Manual (Page 36)

Parameter Value Description
Bit Range
Table size [10:0] System software reads this field to determine the MSI-X Table
size , which is encoded as . For example, a returned
value of 2047 indicates a table size of 2048. This field is read-
only. Legal range is 0–2047 (2 11 ).
Address offset: 0x068[26:16]
Table Offset [31:0] Points to the base of the MSI-X Table. The lower 3 bits of the
table BAR indicator (BIR) are set to zero by software to form a
32-bit qword-aligned offset (4) . This field is read-only.
Table BAR
Indicator
[2:0] Specifies which one of a function’s BARs, located beginning at
0x10 in Configuration Space, is used to map the MSI-X table
into memory space. This field is read-only. Legal range is 0–5.
Pending Bit
Array (PBA)
Offset
[31:0] Used as an offset from the address contained in one of the
function’s Base Address registers to point to the base of the
MSI-X PBA. The lower 3 bits of the PBA BIR are set to zero by
software to form a 32-bit qword-aligned offset. This field is
read-only.
PBA BAR
Indicator
[2:0] Specifies the function Base Address registers, located
beginning at 0x10 in Configuration Space, that maps the MSI-
X PBA into memory space. This field is read-only. Legal range
is 0–5.
Related Information
PCI Express Base Specification Revision 2.1 or 3.0
(4) Throughout this user guide, the terms word, dword and qword have the same meaning that they have in
the PCI Express Base Specification. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.
2014.12.15
Func MSI and MSI-X Capabilities 3-13
Parameter Settings Altera Corporation
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