Altera Arria V Avalon-ST - Manual (Page 40)

Signal Direction Description
rx_st_ready
Input Indicates that the Application Layer is ready to accept data. The
Application Layer deasserts this signal to throttle the data stream.
If
rx_st_ready
is asserted by the Application Layer on cycle
, then
readyLatency
> is a ready cycle, during which
the Transaction Layer may assert
valid
and transfer data.
The RX interface supports a
readyLatency
of 2 cycles.
rx_st_valid
Output Clocks
rx_st_data
into the Application Layer. Deasserts within
2 clocks of
rx_st_ready
deassertion and reasserts within 2 clocks
of
rx_st_ready
assertion if more data is available to send.
rx_st_err Output Indicates that there is an uncorrectable error correction coding
(ECC) error in the internal RX buffer. Active when ECC is
enabled. ECC is automatically enabled by the Quartus II
assembler. ECC corrects single-bit errors and detects double-bit
errors on a per byte basis.
When an uncorrectable ECC error is detected,
rx_st_err
is
asserted for at least 1 cycle while
rx_st_valid
is asserted.
Altera recommends resetting the Arria V Hard IP for PCI
Express when an uncorrectable double-bit ECC error is detected.
Related Information
Avalon Interface Specifications.
Avalon‑ST RX Component Specific Signals
Table 4-2: Avalon-ST RX Component Specific Signals
Signal Direction Description
rx_st_mask
Input
The Application Layer asserts this signal to tell the Hard IP to
stop sending non-posted requests. This signal can be asserted at
any time. The total number of non-posted requests that can be
transferred to the Application Layer after
rx_st_mask
is asserted
is not more than 10.
2014.12.15
Avalon‑ST RX Component Specific Signals 4-3
Interfaces and Signal Descriptions Altera Corporation
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