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Questionable status frequency register, Questionable status acp limit register – GW Instek GSP-930 Programming Manual User Manual

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GSP-930 Programming Manual

46

Questionable Status Frequency Register

Overview

The Questionable Status Frequency Register
indicates if the span or BW settings are invalid.

Bit Summary

Bit Weight Description
5

32

Invalid Span or BW: This is bit is set to 1
when there is an invalid span or
bandwidth (setting) during the
frequency count.

Questionable Status ACP Limit Register

Overview

The Questionable Status ACP Limit Register
Group indicates if any adjacent channel limits
have been tripped.

Bit Summary

Bit Weight Description
0

1

Main Channel High Fail: This bit is set
to 1 when the Main CH HLimit has been
violated.

1

2

Main Channel Low Fail: This bit is set to
1 when the Main CH LLimit has been
violated.

2

4

Adj1 High Fail: This bit is set to 1 when
the ADJCH 1 HLimit has been violated.

3

8

Adj1 Low Fail: This bit is set to 1 when
the ADJCH 1 LLimit has been violated.

4

16

Adj2 High Fail: This bit is set to 1 when
the ADJCH 2 HLimit has been violated.

5

32

Adj2 Low Fail: This bit is set to 1 when
the ADJCH 2 LLimit has been violated.

6

64

Adj3 High Fail: This bit is set to 1 when
the ADJCH 3 HLimit has been violated.

7

128

Adj3 Low Fail: This bit is set to 1 when
the ADJCH 3 LLimit has been violated.