Rainbow Electronics ATmega8HVD User Manual

Atmega4hvd atmega8hvd preliminary, Features

Table of contents

Document Outline

Features
1. Pin Configurations
- 1.1 Pin Descriptions
2. Overview
3. Resources
4. Data Retention
5. About Code Examples
6. AVR CPU Core
- 6.1 Overview
- 6.2 ALU – Arithmetic Logic Unit
- 6.3 Status Register
  - 6.3.1 SREG – AVR Status Register
- 6.4 General Purpose Register File
  - 6.4.1 The X-register, Y-register, and Z-register
- 6.5 Stack Pointer
  - 6.5.1 SPH and SPL – Stack pointer High and Low Register
- 6.6 Instruction Execution Timing
- 6.7 Reset and Interrupt Handling
  - 6.7.1 Interrupt Response Time
7. AVR Memories
- 7.1 Overview
- 7.2 In-System Reprogrammable Flash Program Memory
- 7.3 SRAM Data Memory
  - 7.3.1 Data Memory Access Times
- 7.4 EEPROM Data Memory
  - 7.4.1 EEPROM Read/Write Access
- 7.5 I/O Memory
- 7.6 Register Description
8. System Clock and Clock Options
- 8.1 Clock Systems and their Distribution
- 8.2 Clock Sources
- 8.3 Calibrated Fast RC Oscillator
- 8.4 Slow RC Oscillator
- 8.5 Ultra Low Power RC Oscillator
- 8.6 CPU, I/O, Flash, and ADC Clock
- 8.7 Watchdog Timer and Battery Protection
- 8.8 Clock Startup Sequence
- 8.9 Clock Output
- 8.10 System Clock Prescaler
- 8.11 ADC Clock Prescaler
- 8.12 OSI – Oscillator Sampling Interface
- 8.13 Register Description
9. Power Management and Sleep Modes
- 9.1 Sleep Modes
- 9.2 Idle Mode
- 9.3 ADC Noise Reduction
- 9.4 Power-save Mode
- 9.5 Power-off Mode
- 9.6 Power Reduction Register
- 9.7 Minimizing Power Consumption
- 9.8 Register Description
  - 9.8.1 SMCR – Sleep Mode Control Register
  - 9.8.2 PRR0 – Power Reduction Register 0
10. System Control and Reset
- 10.1 Resetting the AVR
- 10.2 Reset Sources
- 10.3 External Reset
- 10.4 Watchdog Reset
- 10.5 Black-out Detection
- 10.6 ATmega4HVD/8HVD Start-up Sequence
  - 10.6.1 Start-up with one FET connected
  - 10.6.2 Start-up with two FETs connected
- 10.7 Watchdog Timer
  - 10.7.1 Features
- 10.8 Register Description
  - 10.8.1 MCUSR – MCU Status Register
  - 10.8.2 WDTCSR – Watchdog Timer Control Register
11. Interrupts
- 11.1 Interrupt Vectors in ATmega4HVD/8HVD
12. External Interrupt
- 12.1 Register Description
13. High Voltage I/O Ports
- 13.1 High Voltage Ports as General Digital Outputs
  - 13.1.1 Configuring the Pin
  - 13.1.2 Reading the Pin
- 13.2 Alternate Port Functions
  - 13.2.1 Alternate Functions of Port C
- 13.3 Register Description
  - 13.3.1 PORTC – Port C Data Register
  - 13.3.2 PINC – Port C Input Pins Address
14. Low Voltage I/O-Ports
- 14.1 Overview
- 14.2 Low Voltage Ports as General Digital I/O
- 14.3 Alternate Port Functions
  - 14.3.1 Alternate Functions of Port B
- 14.4 Register Description
15. Timer/Counter0 and Timer/Counter1 Prescalers
- 15.1 Overview
- 15.2 Internal Clock Source
- 15.3 Prescaler Reset
- 15.4 External Clock Source
- 15.5 Register Description
  - 15.5.1 TCCRnB – Timer/Counter n Control Register B
  - 15.5.2 GTCCR – General Timer/Counter Control Register
16. Timer/Counter(T/C0,T/C1)
- 16.1 Features
- 16.2 Overview
  - 16.2.1 Registers
  - 16.2.2 Definitions
- 16.3 Timer/Counter Clock Sources
- 16.4 Counter Unit
- 16.5 Modes of Operation
- 16.6 Input Capture Unit
- 16.7 Output Compare Unit
  - 16.7.1 Compare Match Blocking by TCNT0 Write
  - 16.7.2 Using the Output Compare Unit
- 16.8 Timer/Counter Timing Diagrams
- 16.9 Accessing Registers in 16-bit Mode
  - 16.9.1 Reusing the temporary high byte register
- 16.10 Register Description
17. ADC - Analog-to-Digital Converter
- 17.1 Features
- 17.2 Operation
- 17.3 Starting a Conversion
- 17.4 Conversion Timing
- 17.5 ADC Voltage Reference
- 17.6 ADC Noise Canceler
- 17.7 ADC Conversion Result
  - 17.7.1 Temperature Measurement using the internal temperature sensor – TBD
- 17.8 Register Description
18. Voltage Reference
19. Voltage Regulator
- 19.1 Features
- 19.2 Overview
- 19.3 Battery Pack Short mode
- 19.4 Regulator Force mode
- 19.5 Register Description
  - 19.5.1 ROCR – Regulator Operating Condition Register
20. Battery Protection
- 20.1 Features
- 20.2 Overview
- 20.3 Short-circuit Protection
- 20.4 Discharge Over-current Protection
- 20.5 Charge Over-current Protection
- 20.6 External Protection Input
- 20.7 Battery Protection CPU Interface
- 20.8 Register Description
21. FET Control
- 21.1 Overview
  - 21.1.1 FETs disabled during reset
- 21.2 FET Driver
  - 21.2.1 Features
  - 21.2.2 Overview
- 21.3 DUVR – Deep Under-Voltage Recovery Mode operation
- 21.4 Register Description
  - 21.4.1 FCSR – FET Control and Status Register
22. debugWIRE On-chip Debug System
- 22.1 Features
- 22.2 Overview
- 22.3 Physical Interface
- 22.4 Software Break Points
- 22.5 Limitations of debugWIRE
- 22.6 Register Description
  - 22.6.1 DWDR – debugWire Data Register
23. Self-Programming the Flash
- 23.1 Overview
- 23.2 Performing Page Erase by SPM
- 23.3 Filling the Temporary Buffer (Page Loading)
- 23.4 Performing a Page Write
- 23.5 Addressing the Flash During Self-Programming
- 23.6 Register Description
  - 23.6.1 SPMCSR – Store Program Memory Control and Status Register
24. Memory Programming
- 24.1 Program And Data Memory Lock Bits
- 24.2 Fuse Bits
- 24.3 Signature Bytes
- 24.4 Calibration Bytes
- 24.5 Page Size
- 24.6 Serial Downloading
  - 24.6.1 Serial Programming Algorithm
  - 24.6.2 Serial Programming Instruction set
- 24.7 High-voltage Serial Programming
- 24.8 High-voltage Serial Programming Algorithm
25. Operating Circuit
26. Electrical Characteristics
- 26.1 DC Characteristics
- 26.2 Oscillator Characteristics
- 26.3 System and Reset Characteristics
- 26.4 External Interrupts Characteristics
- 26.5 General I/O Lines Characteristics
- 26.6 Programming Characteristics
  - 26.6.1 Serial Programming
  - 26.6.2 High-voltage Serial Programming
27. Typical Characteristics – TBD
28. Register Summary
29. Instruction Set Summary
30. Ordering Information
- 30.1 ATmega4HVD
- 30.2 ATmega8HVD
31. Packaging Information
- 31.1 18M1
32. Errata
- 32.1 ATmega4HVD
  - 32.1.1 All revisions
- 32.2 ATmega8HVD
  - 32.2.1 All revisions
33. Datasheet Revision History
- 33.1 Rev. B - 09/08
- 33.2 Rev. A - 09/08
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