Rainbow Electronics ATmega8HVD - Manual (Page 34)

34
8052B–AVR–09/08
ATmega4HVD/8HVD
Notes: 1. Discharge FET must be switched off for Charger Detect to be enabled.
2. RCOSC_FAST runs in Power-save mode if DUVR mode is enabled. It also runs for approxi-
mately 128 ms after C-FET/D-FET has been enabled.
3. Runs only when OSI is enabled and RCOSC_SLOW is selected as source for OSI.
9.2 Idle Mode
When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing all peripheral functions to continue operating. This sleep
mode basically halts clk
CPU
and clk
FLASH
, while allowing the other clocks to run. Idle mode
enables the MCU to wake up from external triggered interrupts as well as internal ones like the
Timer Overflow interrupt.
9.3 ADC Noise Reduction
When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, Watchdog Timer (WDT), Cur-
rent Battery Protection (CBP), and the Ultra Low Power RC Oscillator (RCOSC_ULP) to
continue operating. This sleep mode basically halts clk
I/O
, clk
CPU
, and clk
FLASH
, while allowing
the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements.
9.4 Power-save Mode
When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-
save mode. In this mode, the internal Fast RC Oscillator (RCOSC_FAST) is stopped, while
Watchdog Timer (WDT), Current Battery Protection (CBP) and the Ultra Low Power RC Oscil-
lator (RCOSC_ULP) continue operating.
This mode will be the default mode when application software does not require operation of
CPU, Flash or any of the peripheral units running at the Fast internal Oscillator
(RCOSC_FAST).
Note that if a level triggered interrupt is used for wake-up from Power-save mode, the changed
level must be held for some time to wake up the MCU. Refer to
”External Interrupt” on page 53
for details.
When waking up from Power-save mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined in
”Clock Sources” on page 23 .
VREG X X X X
CHARGER_DETECT (1) X X X X X
VREGMON X X X
OSI X X
Table 9-2. Active modules in different Sleep Modes (Continued)
Module
Mode
Active Idle
ADC Noise
Reduction Power-save Power-off